Step-up rectifier circuit

ABSTRACT

A step-up rectifier circuit includes first and second input terminals for applying AC outputs of opposite polarities, a third input terminal connected between the first and second input terminals, a plurality of rectifier elements connected between the third input terminal and a first output terminal, a plurality of output capacitors connected parallel to the rectifier elements, a second output terminal connected to a node between said output capacitors, a plurality of first capacitors connected between nodes between those of said rectifying elements located between the first output terminal and the second output terminal and a plurality of second capacitors connected between nodes between those of the rectifying elements which are between the second output terminal and the third input terminal, wherein the ratio between the capacitance of the first capacitors and the second capacitors is defined such that the ratio between the output voltages at individual output terminals can be made constant, regardless of whether they are loaded or unloaded.

BACKGROUND OF THE INVENTION

The present invention relates to a step-up rectifier circuit and, as disclosed herein, to a step-up rectifier circuit which multiplies the input voltage and can generate different output voltages and currents at a plurality of output terminals, by using a plurality of diodes and a plurality of capacitors.

DESCRIPTION OF THE PRIOR ART

As is well-known in the art, a step-up rectifier circuit constructed with a plurality of diodes and capacitors usually has a high internal impedance. As a result, the step-up rectifier circuit has the defect that the output voltage varies widely with changes in load. When an output voltage is provided from an intermediate portion of the rectifier circuit, it has a very strong influence upon the voltage at another output terminal, so that it is difficult to keep the ratio of two voltages at a constant regardless of the load condition. As a result, it is impossible for the step-up rectifier circuit to stabilize individual output voltages when the rectifier circuit is made to generate multiple outputs.

SUMMARY OF THE INVENTION

An object of this invention is, therefore, to provide a step-up rectifier circuit in which the ratio between the output voltages at individual output terminals can be made constant, regardless of the load conditions, and which can readily generate sufficiently stabilized output voltages at the individual output terminals.

Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned from the practice of the invention. The objects and advantages may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

In order to achieve the objects of the present invention as embodied and broadly described herein, a step-up rectifier circuit is provided for multiplying the input voltage applied to said rectifier circuit, comprising first and second input terminals for supplying AC inputs of opposite polarities, a third input terminal connected between said first and second input terminals, rectifier means provided with a plurality of rectifying elements connected in series with said third input terminal and aligned in the same direction of rectification, a plurality of series-connected output capacitors having one end connected to said third input terminal and connected in parallel to said plurality of rectifying elements, a first output terminal connected to the other end of said series-connected output capacitors, a second output terminal connected to a node between said output capacitors, a plurality of first capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said first output terminal and said second output terminal, and a plurality of second capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said second output terminal and said third input terminal, wherein the ratio between the total capacitance C_(A) of said first capacitors and the total capacitance C_(B) of said second capacitors is defined by the following equation: ##EQU1## in which I₁ designates the current flowing through the first output terminal, I₂ designates the sum of the currents flowing through said first output terminal and said second output terminal, n₁ designates one half of the number of said first capacitors, and n₂ designates one half of the number of said second capacitors.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of one embodiment of the step-up rectifier circuit constructed according to the present invention;

FIG. 2 is a circuit diagram used to explain the operation of the embodiment of the present invention;

FIG. 3 is a circuit diagram of another embodiment of the step-up rectifier circuit constructed according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described in connection with two embodiments thereof, and with reference to the accompanying drawings.

In FIG. 1, AC power supply A is connected to the primary winding n₁ of a transformer T. The secondary winding n₂ of this transformer T is provided with a middle tap m. Two terminals a, b of the secondary winding n₂ and the middle tap m of the transformer provide first to third input terminals, so that AC inputs of opposite polarities are supplied to the two terminals a,b of the secondary winding n₂. The tap m, acting as the third input terminal, is grounded. A plurality of diodes D₁ to D₁₅ are connected in series between the tap m and a first output terminal P₁ so that their rectification directions are identical. More specifically, the anode of diode D₁ is connected to the tap m, and the cathode of diode D₁₅ is connected to the first output terminal P₁.

A plurality of capacitors C₁ to C₅ are connected between one side a of the secondary winding n₂ of the transformer T acting as the first input terminal and predetermined nodes of the diodes D₁ to D₁₅. More specifically, the capacitors C₁ and C₂ are connected in series between one side a of the secondary winding n₂ and the node j between diodes D₅ and D₆ ; and a node between the capacitors C₁ and C₂ is connected to the node f between diodes D₂ and D₃. The capacitors C₃, C₄ and C₅ are connected in series between one side a of the secondary winding n₂ and the node x between diodes D₁₄ and D₁₅. The node between capacitors C₃ and C₄ is connected to the node n between diodes D₈ and D₉, and the node between capacitors C₄ and C₅ is connected to the node u between diodes D₁₁ and D₁₂.

Five output capacitors C₆ to C₁₀ are connected between the anode of diode D₁ and the cathode of diode D₁₅. As shown, the node between capacitors C₆ and C₇ is connected to the node g between diodes D₃ and D₄, and the node between capacitors C₇ and C₈ is connected to the node k between diodes D₆ and D₇. The node between capacitors C₈ and C₉ is connected to the node s between diodes D₉ and D₁₀, and the node between capacitors C₉ and C₁₀ is connected to the node v between diodes D₁₂ and D₁₃.

A plurality of capacitors C₁₁ to C₁₅ are connected between the other side b of the secondary winding n₂ of the transformer T, which acts as a second input terminal, and predetermined nodes between diodes D₁ to D₁₅. More specifically, capacitors C₁₁ and C₁₂ are connected in series between the other side b of the secondary winding n₂ and the node h between diodes D₄ and D₅. The node between these capacitors C₁₁ and C₁₂ is connected to the node e between diodes D₁ and D₂. The capacitors C₁₃, C₁₄ and C₁₅ are connected in series between the other side b of the secondary winding n₂ and the node w between diodes D₁₃ and D₁₄. Of these, the node between capacitors C₁₃ and C₁₄ is connected to the node l between diodes D₇ and D₈, and the node between capacitors C₁₄ and C₁₅ is connected to the node t between diodes D₁₀ and D₁₁.

To provide a general explanation, the following designations are made for the construction described above. The current output from the first output terminal P₁ is designated by i₁ (A); the current output from a node P₂ (which will be referred to as the "second output terminal P₂ ") between capacitors C₇ and C₈ is designated by i₂ (A); the number of circuit steps between the grounded portion and the second output terminal P₂ (i.e., the number of capacitors connected between the nodes between rectifying elements located between the tap m and the second output terminal P₂ and the first input terminal a or the second input terminal b) is designated by N₂, wherein N₂ =2 in FIG. 1; the number of steps between the output terminal P₂ and the output terminal P₁ (i.e., the number of capacitors connected in series between the nodes between the rectifying elements located between the output terminal P₂ and P₁ and the first or second input terminal) is designated by N₁ , wherein N₁ =3 in FIG. 1; the voltage between the grounded portion and the output terminal P₂ is designated by E₂ (V); the voltage between the output terminal P₂ and the output terminal P₁ is designated by E₁ (V); the secondary voltage of the transformer T is designated by E₀ (V); and the frequency of the power supply is designated by F(=1/T) (HZ). The capacitances of the capacitors C₁, C₂, C₆, C₇, C₁₁ and C₁₂, constituting the circuit from the grounded portion to the output terminal P₂, are designated by C_(B) (F), and the capacitances of the capacitors C₃ to C₅, C₈ to C₁₀ and C₁₃ to C₁₅, constituting the circuit from the output terminal P₂ to the output terminal P₁, are designated by C_(A) (F).

If this circuit is operated with a full output but zero current, i.e., under no load, the voltages E₁ and E₂ are expressed by the following equations:

    E.sub.1 =2N.sub.1 E.sub.0                                  (1)

    E.sub.2 =2N.sub.2 E.sub.0                                  (2)

Before the steps of deducing the above equation are explained, the operation of the circuit described above will be described in the following.

First, the other side b of its secondary winding n₂ is at a voltage of -E₀ /2 with respect to ground potential. In this case, diode D₁ is turned on so that capacitor C₁₁ is charged to a voltage E₀ /2, in the direction such that its node e becomes positive, by a current which flows through node m, diode D₁, node e, capacitor C₁₁ and the output terminal b. Next, the one side a of the secondary winding n₂ is at a voltage of -E₀ /2 with respect to ground potential. In this case, diode D₂ is turned on so that capacitor C₁ is charged to a voltage 3/2E₀ which is the sum of the output voltage E₀ of the secondary winding and the charged voltage E₀ /2, in the direction such that node f becomes positive, by a current which flows through the output terminal b, capacitor C₁₁, node e, diode D₂, node f, capacitor C₁ and terminal a.

Next, the output terminal b of the secondary winding is at a voltage of -E₀ /2. In this case, diode D₃ is turned on so that capacitor C₆ is charged to a voltage of 2E₀ which is the sum of the output voltage E₀ /2 between the terminal a and node m of secondary winding and the charged 3/2E₀ of capacitor C₁, in the direction such that node g becomes positive, by a current which flows through the output terminal a, capacitor C₁, node f, diode D₃, capacitor C₆ and node m. At the same time when the diode D₃ is turned on, the diode D₄ is turned on so that capacitor C₁₂ is charged to a voltage of 2E₀ which is the sum of the output voltage E₀ of the secondary winding, the charged 3/2E₀ of capacitor C₁ and the charged -E₀ /2 (a charge direction which is the reverse of that at the capacitor C₁₂) of capacitor C₁₁, in the direction such that node h becomes positive, by a current which flows through node m, terminal a, capacitor C₁, diode D₃, diode D₄, capacitor C₁₂, capacitor C₁₁ and the terminal b.

Next, the output terminal b of the secondary winding is at a voltage of E₀ /2. In this case, the diode D₅ is turned on so that capacitor C₂ is charged to a voltage of 2E₀ which is the sum of the output voltage E₀ of the secondary winding, the charged voltage E₀ /2 of capacitor C₁₁, the charged voltage of 2E₀ of capacitor C₁₂ and the charged voltage -3/2E₀ of capacitor C₁, in the direction such that node j is positive, by a current which flows through the secondary winding n₂, capacitor C₁₁, capacitor C₁₂, diode D₅, capacitor C₂, and capacitor C₁. Next, the output terminal a of the secondary winding is at a voltage of E₀ /2. In this case, the diode D₆ is turned on so that capacitor C₇ is charged to a voltage of 2E₀ which is the sum of the output voltage E₀ /2 between the terminal a and node m of secondary winding n₂, the charged voltage 3/2E₀ of capacitor C₁, the charged voltage 2E₀ of capacitor C₂ and the charged voltage -2E₀ of capacitor C₆, in the direction such that node k becomes positive, by a current which flows through terminal a, capacitor C₁, capacitor C₂, diode D₆, capacitor C₇, capacitor C₆ and node m.

At the same time the diode D₇ is turned on so that capacitor C₁₃ is charged to a voltage of 9/2E₀ which is the sum of the output voltage E₀ of secondary winding n₂, the charge voltages 3/2E₀ of capacitor C₁ and the charged voltage 2E₀ of capacitor C₂, in the direction such that node l becomes positive, by a current which flows through the secondary winding n₂, capacitors C₁, C₂, diode D₆, D₇, and capacitor C₁₃.

Next, the terminal b of the secondary winding n₂ is at a voltage of E₀ /2. In this case, diode D₈ is turned on so that capacitor C₃ is charged to a voltage of 11/2E₀ which is the sum of the output voltage E₀ of the secondary winding n₂ and the charged voltage 9/2E₀ of capacitor C₁₃, in the direction such that node n becomes positive, by a current which flows through the secondary winding n₂, capacitor C₁₃, diode D₈ and capacitor C₃. Next, the terminal a of the secondary winding is at a voltage of E₀ /2. In this case, diode D₉ is turned on so that capacitor C₈ is charged to a voltage of 2E₀ which is the sum of the output voltage E₀ /2 between the terminal a and node m, the charged voltage 11/2E₀ of capacitor C₃ and the charged voltage -2E₀, -2E₀ of capacitor C₇ and C₆, respectively, in the direction such that node s becomes positive, by a current which flows through node m, terminal a, capacitor C₃, diode D₉ and capacitors C₈, C₇, C₆.

At the same time, diode D₁₀ is turned on. In this case, capacitor C₁₄ is charged to a voltage of 2E₀ which is the sum of the output voltage E₀ of the secondary winding n₂ the charged voltage 11/2E₀ of capacitor C₃ and the charged voltage -9/2E₀ of capacitor C₁₃, in the direction so that node t becomes positive, by a current which flows through the secondary winding n₂, capacitor C₃, diodes D₉, D₁₀, and capacitors C₁₄, C₁₃.

Next, the terminal b of the secondary winding n₂ is at a voltage E₀ /2. In this case, the diode D₁₁ is turned on so that a capacitor C₄ is charged to a voltage of 2E₀ which is the sum of the voltage E₀ of the secondary winding n₂, charged voltages 9/2E₀, 2E₀ of capacitors C₁₃, C₁₄, and the charged voltages -11/2E₀ of capacitor C₃, in the direction such that node u becomes positive, by a current which flows through the secondary winding n₂, capacitors C₁₃, C₁₄, diode D₁₁, and capacitors C₄, C₃.

Next, the terminal a is positive. In this case, diode D₁₂ and diode D₁₃ are turned on. As a result, capacitor C₉ is charged to a voltage 2E₀ which is the sum of the output voltage E₀ /2 between the terminal a and node m, the charged voltages 11/2E₀, 2E₀ of capacitors C₃, C₄ and the charged voltages -2E₀, -2E₀, -2E₀ of capacitors C₈, C₇, C₆, in the direction such that node v becomes positive, by a current which flows through node m, terminal a, capacitors C₃, C₄, diode D₁₂, capacitors C₉, C₈, C₇, C₆. At the same time, capacitor C₁₅ is charged to a voltage 2E₀ which is the sum of the voltage E₀ of the secondary winding n₂, the charged voltages 11/2E₀, 2E₀ of capacitors C₃, C₄ and the charged voltages -2E₀, -9E₀ of capacitor C₁₄, C₁₃, in the direction such that node w is positive, by a current which flows through the secondary windings n₂, capacitors C₃, C₄, diodes D₁₂, D₁₃ and capacitors C₁₅, C₁₄, C₁₃.

Next, the terminal b of the secondary winding is positive. In this case, diode D₁₄ is turned on so that a capacitor C₅ is charged to a voltage 2E₀ which is the sum of the output voltage E₀ of the secondary winding n₂, the charged voltage 9/2E₀, 2E₀, 2E₀ of capacitors C₁₃, C₁₄, C₁₅ and the charged voltage -2E₀, -11/2E₀ of capacitors C₄, C₃, in the direction such that node x is positive, by a current which flows through the secondary winding n₂, capacitors C₁₃, C₁₄, C₁₅, diode D₁₄ and capacitors C₅, C₄, C₃. Next, the terminal a is positive. In this case, the diode D₁₅ is turned on so that capacitor C₁₀ is charged to a voltage 2E₀ which is the sum of the output voltage E₀ /2 between terminal a and node m, the charged voltages 11/2E₀, 2E₀, 2E₀ of capacitors C₃, C₄, C₅ and the charged voltages -2E₀,-2E₀, -2E₀, -2E₀ of capacitors C₉, C₈, C₇, C₆, in the direction such that the output terminal is positive, by a current which flows through node m, terminal a, capacitors C₃, C₄, C₅, diode D₁₅ and capacitors C₁₀, C₉, C₈, C₇, C₆.

As described above, each of the output capacitors C₆ to C₁₀ is charged to voltage 2E₀ which is twice the output voltage E₀ of the secondary winding n₂. The voltages E₁ and E₂ are obtained by summing the voltages on the capacitors C₆ and C₇ for voltage E₂, and capacitors C₈ to C₁₀ for voltage E₁. Thus, the voltages obtained are as expressed in equations (1) and (2) above.

The equations (1) and (2) are formed under no load. When load current flows from the output terminals P₂ and P₁, a voltage drop E_(d) is established, which will now be considered with reference to FIG. 2.

In FIG. 2, the mean value of the load current flowing during one period, T (=1/f) is designated by I (A), and the voltage drop which occurs during one period in an output capacitor of a capacity C (F) is designated by e₀ (V). The capacitances of the individual capacitors are assumed to be equal.

The following conditions (a) to (c) hold for FIG. 2:

(a) A load current flows through the output capacitors C₁₁, C₁₂ and C₁₃ connected in series, so that each output capacitor produces an equal voltage drop e₀ of predetermined value.

(b) The voltage drops during one period generated in capacitors C₁₁, C₁₂ and C₁₃ at the instant within that period at which a point a becomes positive are supplied by capacitors C₂₁, C₂₂ and C₂₃ (i.e., they are charged to compensate for discharges due to the current flows).

(c) The voltage drops during one period, generated in capacitors C₂₁, C₂₂ and C₂₃ at the instant within that period at which a point b becomes positive are supplied by capacitors C₃₁, C₃₂ and C₃₃.

As a result, the voltage drops in the individual capacitors during one period are as follows:

C₁₁, C₁₂ and C₁₃ : e₀,

C₂₁ : e₀ (i.e., the voltage drop due to the supply of C₁₁).

C₃₁ : e₀ (i.e., the voltage drop due to the supply of C₂₁)

C₂₂ : 2e₀, (i.e., the voltage drop due to the supply of C₁₂ and C₃₁)

C₃₂ : 2e₀, (i.e., the voltage drop due to the supply of C₂₂)

C₂₃ : 3e₀, (i.e. the voltage drop due to the supply of C₁₃ and C₃₂), and

C₃₃ : 3e₀, (i.e. the voltage drop due to the supply of C₂₃).

The total voltage drops are the sums of the voltage drops in the individual capacitors and are as follows:

C₃₃ : 3e₀, C₂₃ : 6e₀, C₃₂ : 8e₀, C₂₂ : 10e₀, C₃₁ : 11e₀, and C₂₁ : 12e₀.

The output capacitor C₁₁ is supplied by the capacitor C₂₁ so that its voltage drop after the current supply is 12e₀.

Similarly output capacitors C₁₂ and C₁₃ have voltage drops of 10e₀ and 6e₀, respectively.

The values of the voltage drops in the output capacitors C₁₁, C₁₂ and C₁₃ can be broken down as follows:

C₁₁ : (2×3+2×2+2×1)e₀,

C₁₂ : (2×3+2×2)e₀, and

C₁₃ : (2×3)e₀.

In the above three equations, the underlined numerals 3 correspond to the number of capacitors C₂₁, C₂₂ and C₂₃, or C₃₁, C₃₂ and C₃₃ connected between point a or b and nodes between rectifying elements. Therefore, if the number of capacitors connected between point a or b and nodes between rectifying elements is generally designated by n, the voltage drops in the voltage capacitors can be expressed by the following equations:

    C.sub.11 :{2n+2×(n-1)+2×(n-2)}e.sub.0          (a),

    C.sub.12 :{2n+2×(n-1)}e.sub.0                        (b), and

    C.sub.13 : 2n e.sub.0                                      (c).

The total voltage drop resulting from the flow of the load current is the sum of the voltage drops in the individual capacitors. Generally speaking, therefore, the total voltage drop E_(d) is expressed by the following equation when there are three output capacitors:

    E.sub.d ={2n×3+2(n-1)(3-1)+2(n-2)(3-2)}e.sub.0,

wherein

the underlined numerals 3 designate the number of output capacitors.

If the number of capacitors connected between point a or b and nodes between rectifying elements is designated by n, the total voltage drop in the output capacitors is expressed by the following equation when the voltage drops expressed by Equations (a), (b) and (c) are extended to the case of a number n of output capacitors:

    E.sub.d ={2n.sup.2 +2(n-1).sup.2 +2(n-2).sup.2 +2(n-3).sup.2 . . . }e.sub.0.

This equation can be rewritten in the following form: ##EQU2##

In above equation (3),

    e.sub.0 =Q/c=IT/c=1/C.sub.f

As a result, the voltage drop E_(d), when the load voltage is applied at the output, is expressed by the following equation:

    E.sub.d =(2/3n.sup.3 +n.sup.2 +1/3n)I/C.sub.f              (4),

wherein:

n: number of steps in step-up rectifier circuit,

I: load current (A),

C: capacitance of capacitors (F), and

f: frequency of input power supply (Hz).

Therefore, the voltage drop E_(1d) in the voltage E₁ is expressed by the following equation:

    E.sub.1d =(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.Af (5),

wherein

I₁ =i₁.

On the other hand, the voltage drop E_(2d) in the voltage E₂ is expressed by the following equation, because the voltage drop due to the current i₁ is added to the voltage drop due to the current i₂ :

    E.sub.2d =(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.Bf (6),

wherein

I₂ =i₁ +i₂.

From the above, if the voltage at output terminal P₂ (FIG. 1) under load is designated by E₂, and if the voltage from output terminal P₂ to output terminal P₁ is designated E₁, voltages E₁ and E₂ are expressed by the following equations:

    E.sub.1 =2n.sub.1 E.sub.0 -(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.Af                             (7),

and

    E.sub.2 =2n.sub.2 E.sub.0 -(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.Bf                             (8).

If the secondary voltage E₀ of the transformer T is charged to E₀.spsb.' to compensate for the voltage drop in voltage E₁, the following relationship is obtained from Equations (1) and (7):

    2N.sub.1 E.sub.0 =2N.sub.1 E.sub.0.spsb.' -(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.Af

    E.sub.0.spsb.' =E.sub.0 +1/2N.sub.1 ×(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)1/C.sub.Af                    (9)

When the secondary voltage of the transformer T is designated by E₀.spsb.' (V), the following equation can be deduced from equations (2) and (8), if the voltage E₂ at output terminal P₂ returns to a non-loaded voltage:

    2N.sub.2 E.sub.0 =2N.sub.2 E.sub.0.spsb.' -(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.Bf             (10)

The following equation can be deduced from Equation (9) and (10):

    n.sub.2 /n.sub.1 ×(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.A -(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.B =0                           (11)

Equation (11) can be rewritten in the following form: ##EQU3##

From the above, it can be understood that the voltage at the output terminal P₂ can be stabilized if the ratio of the total capacitances of the capacitors used satisfied equation (12), and if stabilization is conducted by the voltage at the terminal P₁.

According to the embodiment thus far described, the capacitances of the capacitors constituting the step-up rectifier circuit are set according to both the magnitudes of output currents relating to the capacitors on the basis of equation (12), and the number of voltage-multiplication steps in the sections relating to those currents. As a result, if the voltage at the terminal side, i.e., output terminal P₁, is stabilized; the voltage at the middle point, i.e., output terminal P₂, can be stabilized so that a plurality of output voltages can be stabilized.

Another embodiment of the present invention will be described in FIG. 3, where components identical to those in FIG. 1 are indicated by the same reference characters.

As shown in FIG. 3, one terminal of each of capacitors C₁ and C₂ is connected to the node between diodes D₂ and D₃ and the node between diodes D₅ and D₆, respectively, and the other terminals thereof are connected to terminal a of the secondary winding n₂ of the transformer T. One terminal of each of capacitors C₁₁ and C₁₂ is connected to the node between diodes D₁ and D₂ and the node between diodes D₄ and D₅, respectively, and the other terminals thereof are connected to the other terminal b of the secondary winding n₂ of the transformer T. An output which has a voltage to ground of E₃ (V) and a current i₃ (A) is obtained from a node P₃ (which will be referred to as the "output terminal P₃ ") between capacitors C₆ and C₇. The remainder of the circuit of FIG. 3 is constructed in the same manner as the corresponding components shown in FIG. 1.

With this structure the output terminals P₁ and P₂ can be handled in exactly the same way as in the foregoing embodiment, and similar operations may be conducted for output terminals P₂ and P₃ by substituting the relationships of I₁ =i₁ +i₂ and I₂ =i₁ +i₂ +i₃. Effects similar to those of the foregoing embodiment can be obtained by these substitutions.

By using this concept, moreover, the individual output voltages from a circuit with three or more output terminals can be stabilized.

In the embodiments thus far described, the description has concerned the case in which the secondary winding of a transformer provided with a tap is used as first to third input terminals to which an AC voltage is applied. The present invention can also be exemplified by a structure in which the first to third input terminals are connected to an AC power supply directly, i.e., not through a transformer. 

What is claimed is:
 1. A step-up rectifier for multiplying the input voltage applied to said rectifier circuit, comprising first and second input terminals for supplying AC inputs of opposite polarities; a third input terminal connected between said first and second input terminals; rectifier means provided with a plurality of rectifying elements connected in series with said third input terminal and aligned in the same direction of rectification; a plurality of series-connected output capacitors, having one end connected to said third input terminal, and connected in parallel to said plurality of rectifying elements; a first output terminal connected to the other end of said series-connected output capacitors; a second output terminal connected to a node between said output capacitors; a plurality of first capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said first output terminal and said second output terminal; and a plurality of second capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said second output terminal and said third input terminal; wherein the ratio between each capacitance C_(A) of said first capacitors and each capacitance C_(B) of said second capacitors is defined by the following equation: ##EQU4## in which I₁ designates the current flowing through the first output terminal; I₂ designates the sum of the currents flowing through said first output terminal and said second output terminal; n₁ designates one half of the number of said first capacitors; and n₂ designates one half of the number of said second capacitors.
 2. The step-up rectifier circuit as defined in claim 1, wherein said first and second input terminals for supplying AC output of opposite polarities are first and second terminals of a secondary winding of a transformer.
 3. A step-up rectifier circuit for multiplying the input voltage applied to said rectifier circuit, comprising first and second input terminals for supplying AC inputs of opposite polarities; a third input terminal connected between said first and second input terminals; rectifier means provided with a plurality of rectifying elements connected in series with said third input terminal and aligned in the same direction of rectification, a plurality of series-connected output capacitors, having one end connected to said third input terminal, and connected in parallel to said plurality of rectifying elements; a first output terminal connected to the other end of said series-connected output capacitors; a second output terminal connected to a node between said output capacitors; at least a third output terminal connected to a node between said output capacitors which are located between said second output terminal and said third input terminal, a plurality of first capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said first output terminal and said second output terminal; and a plurality of second capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said second output terminal and said third output terminal; wherein the ratio between each capacitance C_(A) of said first capacitors and each capacitance C_(B) of said second capacitors is defined by the following equation: ##EQU5## in which I₁ designates the current flowing through the first output terminal; I₂ designates the sum of the currents flowing through said first output terminal and said second output terminal; n₁ designates one half of the number of said first capacitors; and n₂ designates one half of the number of said second capacitors.
 4. The step-up rectifier circuit as defined in claim 3 wherein said first and second input terminals for applying AC outputs of opposite polarities are first and second terminals of a secondary winding of a transformer. 